1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package with a through-silicon via and a fabrication method thereof.
2. Description of the Related Art
To enable electronic equipment to become smaller, chip packages contained therein have been becoming smaller. One approach for reducing the size of chip packages includes using through-silicon vias in the packaged chips. However, in some situations, a redistribution layer in the through-silicon vias is easily delaminated from the sidewall of the vias during a thermal cycle test. Accordingly, the through-silicon vias also reduce the reliability of the packaged chips.
Thus, a new chip package design and a fabrication method thereof are thus desired.